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TDM-CLK (TDM Bus Clock)
Issue 1 June 2005 2263
Any FAIL The Error Code represents the number of timing slips detected on the
incoming synchronization source since the last slip inquiry was sent to the
Tone-Clock circuit. The incoming synchronization signal can be from one
of the following sources:
1. A DS1 Interface circuit pack, if DS1 Synchronization is administered,
and associated with the circuit pack tested
2.
S8700 MC: A Stratum-3 clock, if that option is administered and the
circuit pack tested was the active Tone-Clock in the PN 1.
3.
S8700 MC: The local oscillator on the master IPSI’s Tone-Clock circuit
or on the master Tone-Clock circuit pack, if it is providing the PN’s
clocking signals
4.
S8700 IP: The local oscillator on the IPSI’s Tone-Clock circuit providing
the media gateway’s clocking signals
5.
S8700 MC: An EXP-INTF circuit pack, if the PN on which the test was
executed does not contain the system’s current synchronization
reference
The Error Code is a variable amount ranging from 1 to 255.
1. Small numbers of slips should not result in service degradation. If the
Error Code is small (1 or 2), rerun the test. If the error only occurs
infrequently, it may be ignored.
2. Otherwise, see Synchronization Troubleshooting in SYNC
(Port-Network Synchronization) on page 2143 of this manual.
PASS The IPSI or Processor/Tone-Clock circuit pack does not detect any timing
slips. This indicates that the incoming synchronization timing source is valid
or that the system’s synchronization reference is an IPSI or Processor/
Tone-Clock circuit pack. Use status synchronization to verify that the
desired synchronization reference is providing timing for the system.
Table 809: Test #149 TDM bus Clock Slip Inquiry Test (continued)
Error
Code
Test
Result
Description / Recommendation
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