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Communication Manager Maintenance-Object Repair Procedures
2170 Maintenance Procedures for Avaya Communication Manager 3.0, Media Gateways and Servers
● Replace the active Expansion Interface circuit pack in the master port network.
● In a CSS configuration, replace the Switch Node Interface circuit pack connected to
the active Expansion Interface circuit pack in the master port network. Use list
fiber-link to determine the Switch Node Interface circuit pack that is connected to
the active Expansion Interface circuit pack in the master port network.
● If the system’s synchronization reference is a Tone-Clock circuit pack or a Stratum-3
clock, follow normal escalation procedures.
If the system’s primary synchronization reference is a DS1 Interface circuit pack,
assign a different DS1 Interface as the primary reference. If the problem persists and
slip errors remain, follow the procedures in the troubleshooting section above.
6. For unduplicated Tone-Clock circuit packs in a slave port network:
● Enter set tone-clock location to switch the Tone-Clock in the master port
network.
● If the problem still exists, enter set tone-clock location to switch the
Tone-Clocks in the master port network back to their previous configuration.
Enter test tone-clock location long to test the Tone-Clock in the master and
slave port networks.
Check the Error Log for TDM-CLK errors and verify that TDM Bus Clock Circuit Status
Inquiry test (#148) passes.
If Test #148 fails with an Error Code 2–32, see TDM-CLK (TDM Bus Clock)
on
page 2252 to resolve the problem. If not, continue with the following steps.
● If the master and slave Tone-Clock circuit packs do not fail TDM Bus Clock Test #150
(TDM Bus Clock PPM Inquiry test), replace the Expansion Interface circuit packs that
have EXP-INTF error 2305.
● If the system synchronization reference is a Tone-Clock circuit pack and the master
Tone-Clock circuit pack fails TDM Bus Clock Test #150, follow the steps listed in
“TDM-CLK” to replace the master Tone-Clock circuit pack.
● If the system’s synchronization reference is a DS1 Interface circuit pack and the
master Tone-Clock circuit pack fails TDM Bus Clock test (#150), the primary or
secondary (if administered) synchronization references are not providing valid timing
signals for the system.
If the primary synchronization reference is providing the system’s timing, check the
synchronization references administered, and follow the steps outlined in note (b
). If
the secondary reference is providing timing, follow note (d
).
● If the slave Tone-Clock circuit pack fails TDM Bus Clock Test #150 but the master
Tone-Clock does not fail this test, the master Tone-Clock circuit pack must be
replaced. Follow the Tone-Clock replacement steps listed in TDM-CLK (TDM Bus
Clock).
● Replace the active Expansion Interface circuit pack in the master port network.