Avaya 03-300430 Home Security System User Manual


  Open as PDF
of 2574
 
Communication Manager Maintenance-Object Repair Procedures
2260 Maintenance Procedures for Avaya Communication Manager 3.0, Media Gateways and Servers
1 FAIL This error means the Tone-Clock circuit framing verification firmware
reports an error in the clock synchronization signal coming into this port
network.
1. If the Tone-Clock circuit reporting the problem is a master clock, then
the system synchronization reference is providing a bad timing
source. See SYNC (Port-Network Synchronization)
on page 2143 or
STRAT-3 (Stratum-3 Clock)
on page 2128 to change the system
synchronization reference.
2. If the Tone-Clock circuit is a slave clock, then the EI to which it is
listening is providing a bad timing source. Follow the diagnostic
procedures specified for TDM-CLK Error Code 2305.
3.
S8700 | 8710 / S8500: If no problem can be found with the incoming
synchronization signal, replace the IPSI or Tone-Clock circuit pack.
See Replacing the IPSI or Tone-Clock Circuit Pack
on page 2337.
2 FAIL This error indicates that Tone-Clock circuit has inaccurately detected loss of
signal on the incoming synchronization timing source.
4
8
FAIL The local oscillator on the Tone-Clock circuit failed.
16
32
FAIL The circuitry on the Processor/Tone-Clock circuit used to detect
synchronization timing errors has failed.
1. Errors 2, 4, 8, 16, and 32 indicate that there is poor synchronization
between port networks and external facilities. It may be noticeable to
the customer in the form of errors in data communications. The
Tone-Clock circuit is defective. See Replacing the IPSI or Tone-Clock
Circuit Pack on page 2337.
64 FAIL This message is only sent when an uplink message has reported the loss
of valid synchronization timing information coming into this port network. It
has been reported in TDM-CLK Error Log entries; one or more of 1025,
1281, 1537, 2049 and 2305.
1. Resolve the errors indicated. No separate corrective action is
required.
Table 808: Test #148 TDM bus Clock Circuit Status Inquiry Test (continued)
Error
Code
Test
Result
Description / Recommendation
2 of 3