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APP - 12
A
PPENDICES
<Example 2>
M30
D451
PLS
D51
M0
D50
SP.DDRD
D0 D100 M10H3E1
SM400
K10MOV
D251K10MOV
M0
X0
M2
D450
SP.DDRD
D400 D500H3E1
M2RST
K10MOV
M1SET
M1
D250
SP.DDRD
D200 D300 M20H3E1
M1RST
M2SET
K0
SM400
D1000
>
DECP
D1000
M10
K0
D1000
>
K0D1000
>
M20
M30
DECP D1000
DECP D1000
D1000
K32
>
D1000INCP
D1000
INCP
D1000
INCP
M10 M11
M11
M20 M21
M21
M30 M31
M31
Read the data from D0 to D100,
and normality complete processing.
Read the data from D0 to D100,
and abnormality complete processing.
Read the data from D200 to D300,
and normality complete processing.
Read the data from D200 to D300,
and abnormality complete processing.
Read the data from D200 to D300,
and normality complete processing.
Read the data from D200 to D300,
and abnormality complete processing.
To self CPU high speed interrupt
accept flag from CPU 1
U3E1 G48.0
To self CPU high speed interrupt
accept flag from CPU 1
U3E1 G48.0
To self CPU high speed interrupt
accept flag from CPU 1
U3E1 G48.0
There is the following restriction in the case as the example 2.
1) The Multiple CPU dedicated instruction of Motion CPU cannot be used
Interrupt program/fixed cycle executive type program and low speed
executive type program. When it is used, an instruction may not work by the
timing.