Filter
Top Products
281
Example In the following example, TERM(48) is used to switch the Programming Console
to TERMINAL mode when 00000 is ON. Be sure that pin 6 of the CPU’s DIP
switch is OFF.
TERM(48)
000
000
000
00000
Address Instruction Operands
00000 LD 00000
00001 TERM(48)
000
000
000
5-25-7 WATCHDOG TIMER REFRESH – WDT(94)
T: Watchdog timer value
# (00 to 63)
Ladder Symbols Definer Data Areas
@WDT(94) TWDT(94) T
Description When the execution condition is OFF, WDT(94) is not executed. When the exe-
cution condition is ON, WDT(94) extends the setting of the watchdog timer (nor-
mally set by the system to 130 ms) by 100 ms times T.
Timer extension = 100 ms x T.
Precautions If the cycle time is longer than the time set for the watchdog timer, 9F will be out-
put to the FAL area and the CPU will stop.
If the cycle time exceeds 6,500 ms, a FALS 9F will be generated and the system
will stop.
Timers might not function properly when the cycle time exceeds 100 ms. When
using WDT(94), the same timer should be repeated in the program at intervals
that are less than 100 ms apart. TIMH(15) should be used only in a scheduled
interrupt routine executed at intervals of 10 ms or less.
Flags There are no flags affected by this instruction.
5-25-8 I/O REFRESH – IORF(97)
St: Starting word
IR 000 to IR 049
Ladder Symbol
E: End word
IR 000 to IR 049
Operand Data Areas
IORF(97)
St
E
Limitations IORF(97) can be used to refresh I/O words allocated to only I/O Units (IR 000 to
IR 039) and Special I/O Units (IR 100 to IR 199) mounted to the CPU or Expan-
sion I/O Racks. It cannot be used for other I/O words, such as I/O Units on Slaves
Racks or Group-2 High-density I/O Units.
St must be less than or equal to E.
Description To refresh I/O words allocated to CPU or Expansion I/O Racks (IR 000 to
IR 030), simply indicate the first (St) and last (E) I/O words to be refreshed.
When the execution condition for IORF(97) is ON, all words between St and E
will be refreshed. This will be in addition to the normal I/O refresh performed dur-
ing the CPU’s cycle.
Special Instructions Section 5-25