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MATLAB I/O 99
Xilinx Blocks
It should be noted there is a valid bit that accompanies the data signal. It is
constrained at the same rate. For more information concerning the valid bit, refer
to the Hardware Handshaking section in Chapter 1 of this manual.
If
Data Rate, Set 'FAST' Attribute
is selected, the OFFSET = IN
constraints described above are produced. In addition, a FAST slew rate attribute
is generated for each IOB. This reduces delay but increases noise and power
consumption. For the previous example, the following additional attributes are
added to the .ucf file
NET "Din<0>" FAST;
NET "Din<1>" FAST;
NET "Din<2>" FAST;
NET "Din_valid" FAST;
• Specify IOB Location Constraints: Checking this option allows IOB
location constraints to be specified.
• IOB Pad Locations, e.g. {'Valid Bit', 'MSB', ...., 'LSB'}:
IOB pin locations can be specified as a cell array of strings in this edit box. The
locations are package-specific. For the above example, if a Virtex-E 2000 in a
FG680 package is used, the location constraints for the Din bus can be specified
in the dialog box as {'A36', 'C36', 'B36', 'D35'}. This is translated
into constraints in the .ucf file in the following way:
# Loc constraints
NET "Din<0>" LOC = "D35";
NET "Din<1>" LOC = "B36";
NET "Din<2>" LOC = "C35";
NET "Din_valid" LOC = "A36";
Other parameters used by this block are described in the Common Parameters section
of the previous chapter.
The Gateway In block cannot be placed in an enabled subsystem in System Generator
v2.1. See the Enabled Subsystems section (within the MATLAB I/O library
documentation) explanation for more details.
Gateway Out
The Xilinx Gateway Out block is output from the Xilinx FPGA part of
your Simulink design. It converts System Generator fixed point data
to Simulink double precision. According to its configuration, it can
either define an output port for the top level of the HDL design
generated by System Generator, or be used simply as a test point that
will be trimmed from the hardware representation.