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118 Xilinx Development System
Xilinx System Generator v2.1 Reference Guide
The Next State Matrix and the and Output Array are composed in the following way:
Figure 3-82: Construction of Next State and Output matrices
The rows of the matrices correspond to the current state. The next state matrix has
one column for each input value.
The output array has only one column, as the input value does not affect the output of
the state machine.
The next state logic and state register in this block are implemented with high speed
dedicated block RAM. The output logic is implemented using a distributed RAM
configured as a lookup table, and therefore has zero latency.
Block Parameters Dialog Box
The block parameters dialog can be invoked by double-clicking the icon in your
Simulink model.
Figure 3-83: Moore State Machine block parameters dialog box
The maximum number of states is limited by the depth of the distributed RAM. For
the Virtex family, the maximum number of states supported is 4K and for Virtex-II it is
64K.