Filter
Top Products
12 Xilinx Development System
Xilinx System Generator v2.1 Reference Guide
Simulink hierarchy into a hierarchical VHDL netlist. In addition, System Generator
creates the necessary command files to create the IP block netlists using CORE
Generator, invokes CORE Generator, and creates project and script files for HDL
simulation, synthesis, technology mapping, placement, routing, and bit stream
generation. To ensure efficient compilation of multi-rate systems, System Generator
creates constraint files for the physical implementation tools. System Generator also
creates an HDL test bench for the generated realization, including test vectors
computed during Simulink simulation.
Arithmetic Data Types
System Generator provides the three arithmetic data types that are of greatest use in
DSP: double precision floating point, and signed and unsigned fixed point numbers.
Floating point data cannot be converted into hardware, but is supported for
simulation and modeling.
The set of signed arbitrary precision fixed point numbers has nice mathematical
properties, allowing for operations that are much cleaner than those on familiar
floating point representations. Operations on floating point numbers entail implicit
rounding on the result, and consequently, desirable algebraic characteristics such as
associativity and distributivity are lost. Both are retained for arbitrary precision fixed
point numbers.
System Generator allows the quantization of the design to be addressed as an issue
separate from the implementation of the mathematical algorithm. The transition from
double precision to fixed point can be done selectively. In practice this means the
designer gets the design working using double precision, then converts to fixed point
incrementally. At all times, these three representations can be freely intermingled
without any changes to the signal flow graph. This mixing is possible because library
building blocks are polymorphic, changing their internal behavior based on the types
of their inputs.
There is another benefit from this scheme in which quantization events are broken out
as separate design parameters. At every point and stage of the design, the designer
can specify how both the overflow and the rounding issues are to be addressed. For
cases of overflow, the designer can choose whether or not saturation should be
applied, and do so in consideration of the hardware cost versus the benefit to the
system design. Saturation is a more faithful reflection of the underlying mathematics,
but more expensive in hardware; wrapping is inexpensive but less faithful. It is also
possible to trap overflow events in the system level simulation, which can be a useful
debugging mechanism in the design of subsystem that are intended never to result in
overflow.
Likewise, when quantizing at the least significant bit, the designer can choose
whether the value should be truncated (with no hardware cost) or rounded under
some particular rule (possibly improving the system design, but with added cost in
hardware).
In System Generator, many operators support full precision outputs, which means that
the output precision is always sufficient to carry out the operation without loss
information. Combined with the data type propagation rules supported in Simulink,
this allows great convenience when designing an algorithm. Naturally, any operator
that increases the output width of its inputs (e.g. an adder) cannot feed back on itself
with full precision.
The designer specifies the translation to fixed precision at key points in the design (in
particular, at gateways from the outside world and in feedback loops), and System