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System Generator 9
Introduction
constructs for simulation, its synthesizable subset is far too restrictive for system
design.
System Generator is a software tool for modeling and designing FPGA-based DSP
systems in Simulink. The tool presents a high level abstract view of a DSP system, yet
nevertheless automatically maps the system to a faithful hardware implementation.
What is most significant is that System Generator provides these services without
substantially compromising either the quality of the abstract view or the performance
of the hardware implementation.
System Generator
Simulink provides a powerful high level modeling environment for DSP systems, and
consequently is widely used for algorithm development and verification. System
Generator maintains an abstraction level very much in keeping with the traditional
Simulink blocksets, but at the same time automatically translates designs into
hardware implementations that are faithful, synthesizable, and efficient.
The implementation is faithful in that the system model and hardware
implementation are bit-identical and cycle-identical at sample times defined in
Simulink. The implementation is made efficient through the instantiation of
intellectual property (IP) blocks that provide a range of functionality from arithmetic
operations to complex DSP functions. These IP blocks have been carefully designed
to run at high speed and to be area efficient. In System Generator, the capabilities of
IP blocks have been extended transparently and automatically to fit gracefully into a
system level framework. For example, although the underlying IP blocks operate on
unsigned integers, System Generator allows signed and unsigned fixed point
numbers to be used, including saturation arithmetic and rounding. User-defined IP
blocks can be incorporated into a System Generator model as black boxes which will
be embedded by the tool into the HDL implementation of the design.
System Level Modeling with System Generator
The creation of a DSP design begins with a mathematical description of the operations
needed and concludes with a hardware realization of the algorithm. The hardware
implementation is rarely faithful to the original functional description --instead it is
faithful enough. The challenge is to make the hardware area and speed efficient while
still producing acceptable results.
In a typical design flow --a flow supported by System Generator-- the following steps
occur:
1. Describe the algorithm in mathematical terms,
2. Realize the algorithm in the design environment, initially using double precision,
3. Trim double precision arithmetic down to fixed point,
4. Translate the design into efficient hardware.
Step 4 is error prone because it can be difficult to guarantee the hardware implements
the design faithfully. System Generator eliminates this concern by automatically
generating a faithful hardware implementation.
Step 3 is error prone because an efficient hardware implementation uses just enough
fixed point precision to give correct results. System Generator does not automate this
step, which typically involves subtle trade off analysis, but it does provide tools to
make the process tractable. You might wonder why it is not possible to eliminate Step