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18 Xilinx Development System
Xilinx System Generator v2.1 Reference Guide
Use of Xilinx Smart-IP Cores by the System Generator
To increase hardware performance, most System Generator blocks are implemented
using Xilinx Smart-IP (Intellectual Property) LogiCOREs. These are hand crafted
modules that make optimal use of FPGA resources to maximize performance. Some
System Generator blocks map onto multiple LogiCOREs, for example, the 1024-point
FFT, maps onto Dual Port Memory blocks as well as the FFT core itself.
Some Xilinx blocks also can be implemented as synthesizable VHDL modules, hence
the LogiCORE is an option. When such a block cannot be implemented as a
LogiCORE, System Generator automatically maps the block onto the synthesizable
module. For example, the Xilinx Negate block generates a LogiCORE if you specify
input of up to 256 bits, but for more than 256 bits the block is realized in synthesizable
VHDL.
Many Xilinx blocks have implementations only as LogiCOREs. The reason for this is
circuit performance. Because they are handcrafted for FPGA implementation,
LogiCOREs have predictable performance in all design contexts. For example, the
Xilinx FIR Filter block can be implemented only as the Distributed Arithmetic FIR
Filter LogiCORE.
During algorithm exploration in Simulink and System Generator, it is common to
iterate through block customization, Simulink simulation, and code generation. When
you incorporate Black Box functionality, you can also add HDL simulation to this
flow. To speed this design cycle, it is possible to instruct System Generator to not
invoke Xilinx CORE Generator to re-generate LogiCOREs that have already been
generated and have not changed. This can be done on individual blocks by the
Generate Core checkbox control, or globally using the System Generator block
parameters dialog box.
Licensed Cores
The System Generator targets a suite of new ready-to-use licensed LogiCORE
algorithms for forward error correction (FEC), which are critical for detecting and
correcting errors in wired and wireless communication systems during transmission
of data to optimize the use of available bandwidth. The new algorithms include Reed-
Solomon Encoder/ Decoder, a Viterbi Decoder, and an Interleaver/De-interleaver.
These cores may be used for communication applications such as broadcast
equipment, wireless LAN, cable modems, xDSL, satellite communications,
microwave networks, and digital TV.
The System Generator allows you to build and simulate your FEC designs in Simulink
using the Xilinx Blockset Communication library. System Generator creates a VHDL
design and testbench that allows you to do a VHDL simulation of the FEC cores. Free
evaluation versions of the FEC cores provide the behavioral models needed for VHDL
simulation. The System Generator will allow you to generate the licensed core using
the Xilinx CORE Generator after you have purchased and installed the FEC cores.
Licensing information, as well as instructions for downloading the cores, can be
found at the Xilinx IP Center:
http://www.xilinx.com/ipcenter/fec_index.htm.