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Hardware Handshaking 13
Introduction
Generator then propagates signal types and precisions as appropriate. The
automatically chosen type is the least expensive that preserves full precision.
Translations from signed to unsigned and vice versa are automatic as well.
System Generator also allows designs to contain elements that cannot be realized in
hardware, but assist development and debugging. Examples of such elements are
signal sources, scopes, and machinery that tracks the divergence between fixed point
and double precision calculations. System Generator automatically discards such
elements when asked to translate to hardware.
Hardware Handshaking
In Simulink, time evolution is defined by sample rates for each block in the system.
There are propagation rules along signals so that not every block need set an explicit
sample period. This is extremely flexible, but has implications for modeling
hardware. Sequential circuits are clocked, and a key aspect of designing, especially
multirate systems, is the interplay between clock and clock enable signals. Although
abstracted, a bit and cycle true simulation must have mechanisms for defining and
controlling clocked behavior in the system model.
Every signal has a fixed point value as defined in the previous section. In addition, it
carries an implicit boolean valid bit that can be used to achieve hardware handshakes
between blocks. For example, upon startup, a pipeline may define its output invalid
until it has flushed its pipe. By inspecting the valid bits of its inputs, a block can
determine how to process its input data.
Multirate Systems
Multirate systems can be implemented in System Generator by using sample rate
conversion blocks for up-sampling and down-sampling. The necessary control logic
is automatically generated when the design is netlisted. Before netlisting, the sample
rates in the system are normalized to integer values; in hardware, the system clock
period corresponds to the GCD of the integer sample periods. Clock enables are used
to activate the hardware blocks at the appropriate moment in time with respect to the
system clock.
Consider for example, the multirate system model shown in the figure below, which
consists of I/O registers, an up-sampler, an anti-aliasing filter, and a down-sampler.
The input signal is up-sampled by a factor of two, and subsequently down-sampled
by a factor of three, giving an overall sample rate conversion by a factor of 2/3. The
ST blocks in the system model extract the sample period from a Simulink signal,
which can then be displayed. In the example, the input sample period is one. In the
generated hardware implementation shown below the system model, each element is
driven by the system clock, with its respective clock enable driven according to its
sample period in the original system model.
Figure 1-2: Example of a multirate system model