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Math 81
Xilinx Blocks
• Polyphase behavior: Decimation, Interpolation, Single rate.
• Latency: specify input sample period latency.
• Hardware Over-Sampling Rate: Hardware clocks per sample. This affects
hardware implementation only, and has no effect on simulation. In multi-channel
mode, this factor will multiply the implicit oversampling factor.
Other parameters used by this block are explained in the Common Parameters section
of the previous chapter.
The FIR filter block cannot be placed in an enabled subsystem in System Generator
v2.1. See the Enabled Subsystems section (within the MATLAB I/O library
documentation) explanation for more details.
Xilinx LogiCORE
The block always uses the Xilinx LogiCORE Distributed Arithmetic FIR Filter V6.0.
The Simulink model operates on a sample in/sample out basis, but the core has the
capability of using serial arithmetic by overclocking. Although this adds latency, it has
the benefit of reducing the hardware required for the filter. Refer to the core datasheet
for more details of the filter modes and parameters.
The core datasheet can be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\da_fir_v6_0\doc\
da_fir.pdf
Math
The Math section of the Xilinx Blockset contains mathematical functions.
Accumulator
The Xilinx Accumulator block implements an adder or subtractor based
scaling accumulator. The block’s current input is accumulated with a
scaled current stored value. The scale factor is a block parameter.
Block Interface
The block has an input b, a reset rst, and an output q. The output must have the
same width as the input data. The output q is calculated as follows:
The output must have the same arithmetic type as the input. The block has latency of
one sample period.
A subtractor based accumulator replaces addition of the current input
b(n)
with
subtraction. The output will have the same arithmetic type and binary point position
as the input. The block always has a latency of one sample period.