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FX3S/FX3G/FX3GC/FX3U/FX3UC Series
Programming Manual - Basic & Applied Instruction Edition
13 High-Speed Processing – FNC 50 to FNC 59
13.5 FNC 54 – HSCR / High-Speed Counter Reset
13.5 FNC 54 – HSCR / High-Speed Counter Reset
Outline
This instruction compares the value counted by a high-speed counter with a specified value at each count, and
immediately resets an external output (Y) when both values become equivalent to each other.
1. Instruction format
2. Set data
3. Applicable devices
S1: "D.b" is available only in FX3U and FX3UC PLCs. However, index modifiers (V and Z) are not available.
S2: The same counter as can be specified also. (Refer to the program example shown later.)
S3: This function is supported only in FX
3G/FX3GC/FX3U/FX3UC PLCs.
S4: This function is supported only in FX
3U/FX3UC PLCs.
Explanation of function and operation
1. 32-bit operation (DHSCR)
When the current value of a high-speed counter (C235 to C255) specified in becomes the comparison value
[ +1, ] (for example, when the current value changes from "199" to "200" or from "201" to "200" if the
comparison value is K200), the bit device is reset (set to OFF) regardless of the operation cycle. In this
instruction, the comparison processing is executed after the counting processing in the high-speed counter.
Operation
When the present value of the high-speed counter C255 changes (counts) from "99" to "100" or from "101" to "100",
Y010 is reset (output refresh).
Operand Type Description Data Type
Data to be compared with the current value of a high-speed counter or word device
number storing the data to be compared
32-bit binary
Device number of a high-speed counter [C235 to C255] 32-bit binary
Bit device number to be reset (set to OFF) when both values become equivalent each
other.
Bit
Oper-
and
Type
Bit Devices Word Devices Others
System User Digit Specification System User
Special
Unit
Index Constant
Real
Number
Charac-
ter String
Pointer
XYMTCSD
.b KnX KnY KnM KnS T C D R
U\G
V Z Modify K H E "
"P
S3 S4
S1 S2
Mnemonic Operation Condition
32-bit Instruction
13 steps DHSCR
Continuous
Operation
16-bit Instruction
Mnemonic Operation Condition
−
FNC 54
HSCR
D
S
1
S
2
D
S
1
S
2
D
S
2
S
2
S
1
S
1
D
=
→
Reset.
Comparison
value
Comparison
source
Output
destination
S
1
S
2
D
K2,147,483,647
FNC 54
DHSCR
S
2
S
1
D
S
2
Command
input
K100 = C255
→
Y010
C255
K2,147,483,647
FNC 54
DHSCR
K100 C255 Y010
Reset.
Comparison
value
Comparison
source
Output
destination
M8000
RUN
monitor