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Z(f) Constant Output Impedance Design
50 315889-002
The impedance plot Z(f) shown in Figure A-2 can be divided up into three major areas
of interest.
• Low frequency, Zero Hz (DC) to the VR loop bandwidth. This is set by AVP and loop
compensation of the VR controller or PWM control IC.
• Middle frequency, VR loop bandwidth to socket inductance rise - This is set by the
bulk capacitors, MLCC capacitors and PCB layout parasitic elements.
• High frequency, controlled by socket inductance and the CPU package design.
The VRM/EVRD designer has control of the low and mid frequency impedance design.
By ensuring these areas meet the load line target impedance in Section 2.2, the system
design will work properly with future CPU package designs.
Figure A-2 shows the impedance vs. frequency network the system in Figure 2-1. This
example consists of 17 560 μF with an ESR of 7 mΩ and ESL of 4 nH per bulk
capacitors, 1
st
PCB impedance of 1.0 μΩ and 0.05 pH between the bulk and 45 10 μF
0805 MLCC, with ESR is 10 mΩ and ESL of 1.1 nH, 2
nd
PCB impedance of 1.0 μΩ and
0.05 pH between the 45 10 μF and the 9 10 μF 0805 MLCC in the socket cavity with ESR
is 10 mΩ and ESL of 1.1 nH, and the LGA771 socket impedance of 330
μΩ and 20 pH.
The resonant point seen at 400 kHz is due to the mis-match between the bulk
capacitors and the MLCC cavity capacitors. Increasing the capacitance values will drop
the magnitude and shift the to a lower resonance frequency. For example, if the 10
μF
capacitors are increased to 22
μF, the resonant peak drops in magnitude to 1.0 mΩ and
at a frequency of 200 kHz. The resonant peak could also be reduced by reducing the
ESL of the bulk capacitors by changing capacitor technology or by adding more bulk
Figure A-2. Z(f) Network Plot with 1.25 mΩ Load Line