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Output Indicators
6 Output Indicators
6.1 Voltage Regulator Ready (VR_Ready) - REQUIRED
The VRM/EVRD VR_Ready signal is an output signal that indicates the start-up
sequence is complete and the output voltage has moved to the programmed VID value.
This signal will be used for start-up sequencing for other voltage regulators, clocks, and
microprocessor reset. This signal is not a representation of the accuracy of the DC
output to its VID value.
The platform VR_Ready signal(s) will be connected to logic to assert CPU or system
PWRGD. The value of the resistor and the pull-up voltage will be determined by the
circuitry on the baseboard that is receiving this signal. Typically a 1 kΩ pull to 3.3 V is
used. This signal should not be de-asserted during dynamic VID operation. It should
remain asserted during normal DC-DC operating conditions and only de-assert for fault
shutdown conditions. It will be an open-collector/drain or equivalent signal. The pull-up
resistor and voltage source will be located on the baseboard. Table 6-1 shows the
VR_Ready pin specification.
6.2 Voltage Regulator Hot (VR_hot#) - PROPOSED
The VRM/EVRD VR_hot# signal is an output signal that is asserted low when a thermal
event is detected in the converter. Assertion of this signal will be used by the system to
minimize damage to the converter due to the thermal conditions. Table 6-2 shows the
VR_hot# signal specification. This signal will be an open-collector/drain or equivalent
signal and needs to be pulled up to an appropriate voltage through a pull-up resistor on
the baseboard. A typical implementation would be a 50 Ω ±5% resistor pulled up to
1.1 V/1.2 V. For platforms using a voltage higher than 1.1 V /1.2 V, a voltage level
translation is required. Processors do not tolerate such voltage levels directly. Consult
the appropriate PDG.
Each customer is responsible for identifying maximum temperature specifications for all
components in the VRM/EVRD design and ensuring that these specifications are not
violated while continuously drawing specified Icc (TDC) levels. In the occurrence of a
thermal event, a thermal sense circuit may assert the processor’s FORCEPR# signal
immediately prior to exceeding maximum VRM, baseboard, and/or component thermal
ratings to prevent heat damage. The assertion may be made through direct connection
Table 6-1. VR_Ready Specifications
Symbol Parameter Min Max Units
I
OL
Output Low Current 1 4 mA
V
OH
Output High Voltage 0.8 3.465 V
V
OL
Output Low Voltage 0 0.4 V
Table 6-2. VR_hot# Specifications
Symbol Parameter Min Max Units
I
OL
Output Low Current 19.9 30 mA
V
OH
Output High Voltage 0.8 3.465 V
V
OL
Output Low Voltage 0 0.4 V