Filter
Top Products
Output Voltage Requirements
16 315889-002
2.4 Processor VCC Overshoot - REQUIRED
The VRM/EVRD 11.0 is permitted short transient overshoot events where Vcc exceeds
the VID voltage when transitioning from a high-to-low current load condition
(Figure 2-2). This overshoot cannot exceed VID + VOS_MAX. The overshoot duration,
which is the time that the overshoot can remain above VID, cannot exceed TOS_MAX.
These specifications apply to the processor die voltage as measured across the remote
sense points and should be taken with the oscilloscope bandwidth setting limited to
20 MHz or 100 MHz, depending what is supported by your particular scope (with
20 MHz preference).
• VOS_MAX = Maximum overshoot voltage above VID = 50 mV
• TOS_MAX = Maximum overshoot time duration above VID = 25 µs
2.5 Impedance vs. Frequency - EXPECTED
Vcc power delivery designs can be susceptible to resonance phenomena capable of
creating droop amplitudes that violate the load line specification. This is due to the
frequency varied PCB, output decoupling and socket impedances from the power plane
layout structures. Furthermore, these resonances may not be detected through
standard time domain validation and require engineering analysis to identify and
resolve.
Impedance vs. Frequency, Z(f) performance simulations of the power delivery network
is a strongly recommended method to identify and resolve these impedances, in
addition to meeting the time domain load line in Section 2.2 and Section 2.3. The
decoupling selection needs to be analyzed to ensure that the impedance of the
decoupling is below the load line target up to the F
BREAK (2 MHz) frequency as defined
in Figure 2-3. Frequency domain load line and overshoot compliance is expected across
the 0 Hz to FBREAK bandwidth. The power delivery frequency response is largely
Figure 2-2. Processor Vcc Overshoot Example Waveform
0 5 10 15 20 25
Time [us]
Voltage [V]
VID - 0.000
VID + 0.050
V
OS
T
OS
T
OS
: Overshoot time above VID
V
OS
: Overshoot voltage above VID