Filter
Top Products
Document: LT0273 MX4428 MXP Engineering / Technical Manual
MXP Technical Description
Issue 1.5 24 March 2006 Page 7-9
7.2.5.2 Data Transmission
Each bit transmitted consists of single cycle of a sinewave of one frequency for a ‘0’ and
another frequency for a ‘1’. Each cycle is made up from a number of discreet samples, with a
5uS spacing between samples. For each sample the digitised value is output on the 68302
CPU onto signals AD1, AD2, AD3, AD4, and AD5. These signals are converted to an analog
voltage “TXDATA” by resistors R72, R73, R74, R75, R76, R77, R82, R81, R80, and R79,
which form a conventional R/2R ladder. Resistor R78 adds a DC offset of about 1.5V to the
TXDATA voltage.
Transistor Q14 is a current sink with the current controlled by the TXDATA voltage. The
varying current develops an AC voltage of 4V p-p across R85. This AC voltage is coupled
onto the gate of Q15 through C53. Q15 provides the DC power for the loop (R85 is too high
a resistance for this purpose). Q15 is a source follower, and its source follows the voltage on
its gate. The circuit of R85, Q15 and associated components can be viewed as a circuit with
about 2 - 4 volts DC drop (at 0 - 400mA load), but which has a high AC impedance
determined by R85. (Somewhat like an inductor in that it has a low DC resistance but high
AC impedance.) This supplies power to the loop but at the same time allows the MXP
transmitter (Q14) and the transmitters in the addressable devices to modulate the voltage for
data transmission.
7.2.5.3 Data Reception
The data on the analog loop is filtered by L9, L10, C30, R32, R33 and C39. C37 provides
DC blocking. D2 and D3 with C40 clamp the incoming voltage to 1.2V p-p. The filtered,
clamped voltage is amplified by Q3 and then sliced by U13A to form a 0 - 5V square wave
from the incoming sinewave. The received data is decoded into 0s and 1s by timing and
software within the CPU. Note that the slice level is about 0.6V from the peaks of the AC
voltage on the loop and not at the mid point of the AC component.
7.2.5.4 Open Circuit Fault Handling
The loop is normally driven from the AL terminals, and not driven by the AR terminals.
Optocoupler OC7 checks that power is reaching the far end of the loop i.e. the AR terminals.
If this is not the case, the CPU will close relay RL2 so that the loop is driven (power and
data) from both ends. Thus a single open circuit will result in all addressable devices still
receiving power and still being able to communicate with the MXP. Two open circuits may
result in loss of power and communications with some devices.
Periodically (every 30 seconds) when the loop is driven from both ends, the CPU will open
the right end relay to check whether the open circuit fault has gone away.
7.2.5.5 Short Circuit Fault Handling
If the CPU finds that the over-current detector described in section
7.2.5.1 is unable to be
reset or is operating repeatedly in a short time, it will try to drive the loop from one end at a
time in case the short is present only when driving from one end of the loop. In this case it
will drive the loop from the other end only. However it will try the faulty end very briefly once
every 30 seconds to see if the fault has gone away.
Note that if there are no isolator bases in the loop, the short will appear from both ends and
all devices will be effectively disconnected.
If there are isolator bases, then after an initial overload which will be reset, the isolators will
isolate the section of the loop with the short. The loop will then appear to have an open
circuit and will be driven by both ends simultaneously as described in section
7.2.5.4. Only
those devices connected to the shorted section will be disconnected.