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MB91401
54
(2) Reset
Note : tcp is internal CPU and clock cycle period for peripheral module.
Parameter
Symbol
Pin Conditions
Value
Unit Remarks
Min Max
Reset input time trstl INITXI
After power
supply &
input clock
stabilization
At unusing of PLL 5 tcp ns
At using of PLL 600 + 1 µs
PLL reset input time tprstl PLLS At using of PLL 1 µs
INITXI
PLLS
trstl, tprstl
Prelminary
2004.11.12