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MB91401
35
(Continued)
Address
Register
Block
+
++
+
0
+
++
+
1
+
++
+
2
+
++
+
3
0000_0060
H
SSR0 [R/W]
00001-00
SIDR0 [R/W]
XXXXXXXX
SCR0 [R/W]
00000100
SMR0 [R/W]
00--0-0-
UART0
0000_0064
H
UTIM0 [R]
00000000
(UTIMR0 [W])
00000000
DRCL0 [W]
--------
UTIMC0 [R/W]
0--00001
U-TIMER0
0000_0068
H
SSR1 [R/W]
00001-00
SIDR1 [R/W]
XXXXXXXX
SCR1 [R/W]
00000100
SMR1 [R/W]
00--0-0-
UART1
0000_0048
H
UTIM1 [R]
00000000
(UTIMR1 [W])
00000000
DRCL1 [W]
--------
UTIMC1 [R/W]
0--00001
U-TIMER1
0000_0070
H
to
0000_01FC
H
Reserved
0000_0200
H
DMACA0
00000000 00000000
[R/W]
0000XXXX XXXXXXXX
DMAC
0000_0204
H
DMACB0
00000000 00000000
[R/W]
00000000 00000000
0000_0208
H
DMACA1
00000000 00000000
[R/W]
0000XXXX XXXXXXXX
0000_020C
H
DMACB1
00000000 00000000
[R/W]
00000000 00000000
0000_0210
H
DMACA2
00000000 00000000
[R/W]
0000XXXX XXXXXXXX
0000_0214
H
DMACB2
00000000 00000000
[R/W]
00000000 00000000
0000_0218
H
DMACA3
00000000 00000000
[R/W]
0000XXXX XXXXXXXX
0000_021C
H
DMACB3
00000000 00000000
[R/W]
00000000 00000000
0000_0220
H
DMACA4
00000000 00000000
[R/W]
0000XXXX XXXXXXXX
0000_0224
H
DMACB4
00000000 00000000
[R/W]
00000000 00000000
0000_0228H
to
0000_023C
H
Reserved
0000_0240
H
DMACR
0XX00000 XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
DMAC
0000_0244
H
to
0000_0300
H
Reserved
0000_0304
H
ISIZE [R/W]
------10
Instruction
Cache
Prelminary
2004.11.12