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MB91401
39
(Continued)
Address
Register
Block
+
++
+
0
+
++
+
1
+
++
+
2
+
++
+
3
010F_0000
H
BSR[R]
00000000
BCR[R/W]
00000000
CCR[R/W]
10000000
ADR[R/W]
1XXXXXXX
I
2
C
010F_0004H
DAR[R/W]
XXXXXXXX
BC2R[R/W]
00XX0000
010F_0008
H
to
010F_FFFF
H
(Reserved)
Address
Register
Block
+
++
+
0
+
++
+
1
+
++
+
2
+
++
+
3
0110_0000
H
DLCR0*
0X000000
DLCR1[R, W]
00000000
DLCR2*
00000000
DLCR3[R/W]
00000000
LAN controller
0110_0004
H
DLCR4*
00000010
DLCR5*
01000001
DLCR6*
10000000
DLCR7*
00000000
0110_0008
H
DLCR8[R/W]
00000000
DLCR9[R/W]
00000000
DLCR10[R/W]
00000000
DLCR11[R/W]
00000000
0110_000C
H
DLCR12[R/W]
00000000
DLCR13[R/W]
00000000
0110_0008
H
MAR8[R/W]
00000000
MAR9[R/W]
00000000
MAR10[R/W]
00000000
MAR11[R/W]
00000000
0110_000C
H
MAR12[R/W]
00000000
MAR13[R/W]
00000000
MAR14[R/W]
00000000
MAR15[R/W]
00000000
0110_0008
H
BMPR10*
00000000
BMPR11*
00000111
0110_000C
H
BMPR12*
00000000
BMPR14*
00000000
0110_0010
H
BMPR8
00000000-00000000
[R/W]
00000000-00000000
0110_0014
H
FILTER_CMD
[R/W]
XXXXXXXX
0110_0018
H
FILTER_STATUS
[R]
XXXXXXXX
0110_001C
H
FILTER_DATA
[R/W]
XXXXXXXX
0110_0020
H
FL_CONTROL
[R/W]
XXXXXXXX
0110_0024
H
FL_SUBNET
[R/W]
XXXXXXXX
Bank 0
Bank 1
Bank 2
Prelminary
2004.11.12