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Chapter 32 USART (LIN / FIFO)
1.Overview
■ USART Interrupts
Table 1-3 Mode Bit Setting
MD1 MD0 Mode Description
0 0 0 Asynchronous (normal mode)
0 1 1 Asynchronous (multiprocessor mode)
1 0 2 Synchronous (normal mode)
1 1 3 Asynchronous (LIN mode)
Table 1-4 USART interrupts
Interrupt
cause
Interrupt
number
Interrupt control register Interrupt Vector
Register name Address Offset Default address
USART04
reception
interrupt
#66 (42
H
) ICR25 0459
H
2F4
H
000FFEF4
H
USART04
transmission
interrupt
#67 (43
H
) ICR25 0459
H
2F0
H
000FFEF0
H