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Chapter 22 Main Oscillation Stabilisation Timer
3.Configuration
3. Configuration
Figure 3-1 Configuration Diagram
Figure 3-2 List of Registers
Note: Refer to “Chapter 24 Interrupt Control (Page No.311)” for the ICR register and the interrupt vector.
Main clock oscillation stability wait timer
Interval time
WS1-0 OSCR:bit 2-1
Setting disable
0
0
1
10
11
0
2
12
F
2
17
/
/
F
2
23
/ F
CL-MAIN
CL-MAIN
CL-MAIN
Timer operation enable
WEN OSCR:bit 5
0
1
Operation stop
Operation enable
Interrupt disable
Interrupt enable
WIE OSCR:bit 6
0
1
Selector
Edge detection
WIF OSCR:bit 7
0
1
Without interrupt request
With interrupt request
WRITE
READ:
0
1
Flag clear
Not affected
1
0
Main clock
Oscillation stability
wait interrupt (#46)
Main clock
(Source oscillation)
23-bit free run timer
012345678910111213141516171819202122
222
4
22
78
2222222222
2
22222
123 56
22
9101112131415161718
19
20
21
22 23
WCL OSCR:bit 2
0
1
Timer clear
Does not affect the operation
Timer clear