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Chapter 31 External Bus
9.SDRAM/FCRAM Interface Operation
Figure 9-8 Using 64 - Mbit SDRAM
When using one SDRAM module with a data width of 16 bits, SDRAMs No. 2, No. 3, and No. 4 are not required
and DQ15 to DQ0 must be left open.
When two SDRAM modules are used with a data width of 16 bits, SDRAMs No. 2 and No. 4 are not required.
When two SDRAM modules are used with a data width of 32 bits, SDRAMs No. 3 and No. 4 are not required.
● Using 32 - bit SDRAM
When the data width is 32 bits: Use one or two SDRAM modules.
Figure 9-9 shows 64-Mbit SDRAM (one bank address and 12 row addresses).
Figure 9-9 Using 64 - Mbit
A11-A0
This LSI
CS7 CS6 SCASSRAS SWE MCLKE
DQMUU
MCLKO DQ31-0
IA11-IA0
SDRAM(No.1)
CS CASRAS WE
CKE DQML CLK
DQ15-DQ0
BA1
SDRAM(No.2)
CS CASRAS WE
CKE DQML CLK DQ15-DQ0
SDRAM(No.3)
CS CASRAS WE
CKE DQML CLK DQ15-DQ0
IA11-IA0
SDRAM(No.4)
CS CASRAS WE
CKE DQML CLK DQ15-DQ0
[15-0]
[31-16]
[15-0]
[31-16]
DQMU
DQMU
DQMU
DQMU
DQMUL
DQMLU
DQMLL
IA11-IA0
IA11-IA0
A15 A14
BA0
BA1BA0
BA1BA0
BA1BA0
A11-A0
This LSI
CS7 CS6 SCASSRAS SWE
MCLKE
DQMUU
MCLKO DQ31-0
IA11-IA0
SDRAM(No.1)
CS CASRAS WE
CKE DQM0 CLK DQ31-DQ0
IA11-IA0
SDRAM(No.2)
CS CASRAS WE
CKE DQM0 CLK DQ31-DQ0
[31-0]
[31-0]
DQM1
DQM1
DQM3 DQM2
DQM3 DQM2
DQMUL
DQMLU
DQMLL
A14
BA
BA