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547
Chapter 31 External Bus
4.Endian and Bus Access
32-bit bus width
Figure 4-10 External bus Access for 32-Bit Bus Width
16-bit bus width
Figure 4-11 External bus Access for 16-Bit Bus Width
32bit
01
(1)
LSBMSB
00
01
(1)
00
10 11
01
(1)
00
10 11
01
(1)
00
10 11
(a) PA1/PA0="00"
(1) Output A1/A0="00"
(b) PA1/PA0="01"
(1) Output A1/A0="00"
(c) PA1/PA0="10"
(1) Output A1/A0="00"
(d) PA1/PA0="11"
(1) Output A1/A0="00"
10 11
1110
01
LSB
MSB
00
(1)
(2)
(1)
(2)
(1)
(2)
(1)
(2)
1110
0100
1110
0100
1110
0100
(a) PA1/PA0="00"
(1) Output A1/A0="00"
(2) Output A1/A0="10"
(b) PA1/PA0="01"
(1) Output A1/A0="00"
(2) Output A1/A0="10"
(c) PA1/PA0="10"
(1) Output A1/A0="00"
(2) Output A1/A0="10"
(d) PA1/PA0="11"
(1) Output A1/A0="00"
(2) Output A1/A0="10"
1110
00
1110
01
10
0100
11
0100
(a) PA1/PA0="00"
(1) Output A1/A0="00"
(b) PA1/PA0="01"
(1) Output A1/A0="00"
(c) PA1/PA0="10"
(1) Output A1/A0="00"
(d) PA1/PA0="11"
(1) Output A1/A0="00"
(1)
(1)
(1)
(1)
1110
0100
1110
0100
1110
0100
1110
0100
(a) PA1/PA0="00"
(1) Output A1/A0="00"
(b) PA1/PA0="01"
(1) Output A1/A0="00"
(c) PA1/PA0="10"
(1) Output A1/A0="00"
(d) PA1/PA0="11"
(1) Output A1/A0="00"
(1)
(1)
(1)
(1)
(A) Word access
(B) Halfword access
(C) Byte access
01 00
11
10