EM78P221/2N
8-Bit Microcontroller with OTP ROM
40 •
Product Specification (V1.0) 10.19.2007
(This specification is subject to change without further notice)
6.7.3.2 Bank 1-RA (CMPCON: Comparator Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EIS1 EIS0 CMPOUT CMPCOS1 CMPCOS0 0 0 0
Bit 5 (CMPOUT): The result of the Comparator output
Bit 4 ~ Bit 3 (CMPCOS1 ~ CMPCOS0): Comparator Select bits
CMPCOS1 CMPCOS0 Function Description
0 0 Comparator is not used. P72, P73 and P71 are normal I/O pins
0 1 P72 and P73 are Comparator input pins and P71 is normal I/O pin
1 0
P72 and P73 are Comparator input pins and P71 is Comparator
output pin (CO)
1 1 Used as OP and P71 is OP output pin (CO)
6.7.3.3 Bank 1-RE (WDT Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDTE 0 PSWE PSW2 PSW1 PSW0 0 CMPIE
Bit 0 (CMPIE): CMPIF interrupt enable bit
0 = Disable CMPIF interrupt
1 = Enable CMPIF interrupt
When the Comparator output status change is used to enter an
interrupt vector or to enter the next instruction, the CMPIE bit must
be set to “Enable“. But actually the comparator output must be read
to latch the status at first. Then the comparator output is compared
to this latch to produce the information of output status change.
6.7.4 Comparator Interrupt
CMPIE must be enabled for the “ENI” instruction to take effect
Interrupt is triggered whenever a change occurs on the comparator output pin
The actual change on the pin can be determined by reading the Bit CMPOUT
CMPIF the comparator interrupt flag, can only be cleared by software
6.7.5 Wake-up from Sleep Mode
If enabled, the comparator remains active and the interrupt remains functional, even
in Sleep mode.
If a mismatch occurs, the interrupt will wake up the device from Sleep mode.
The power consumption should be taken into consideration for the benefit of energy
conservation.
If the function is unemployed during Sleep mode, turn off the comparator before
entering sleep mode.
