EM78P221/2N
8-Bit Microcontroller with OTP ROM
Product Specification (V1.0) 10.19.2007 • 39
(This specification is subject to change without further notice)
NOTE
■ The highest priority of P71/INT1/CO is INT1. When EIS1=0, the working type of
P71/INT1/CO is determined by CMPCOS1 and CMPCOS2.
■ The CO and P71of the P71/CO pins cannot be used at the same time.
■ The P71/CO pin priority is as follows:
The following figure shows the Comparator Output block diagram.
Q
Q
ENEN
D
D
To C0
To
CMPIF
To CMPOUT
CMRD
CMRD
From
other
comparator
RESET
From OP I/
O
Fig. 6-11 Comparator Output Configuration
6.7.3 Using a Comparator as an Operation Amplifier
6.7.3.1 Bank 0-RE (WUCR: Wake-up Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EX1IF 0 0 ICWE 0 CMPWE 0 CMPIF
Bit 2 (CMPWE): Comparator wake-up enable bit
0 = Disable Comparator wake-up
1 = Enable Comparator wake-up
When the Comparator output status change is used to enter an
interrupt vector or to wake-up the EM78P221/2N from sleep, the
CMPWE bit must be set to “Enable“.
Bit 0 (CMPIF): Comparator interrupt flag. Set when a change occurs in the
Comparator output. Reset by software
P71/INT1/CO Pin Priority
High Medium Low
/INT1 CO P71
