Epson Research and Development Page 61
Vancouver Design Center
Hardware Functional Specification S1D13504
Issue Date: 01/01/30 X19A-A-002-18
7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing
Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing
Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing
Symbol Parameter Min Typ Max Units
t1
Memory clock
40 ns
t2
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) 2 t1 ns
RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) 1 t1 ns
t3
Random read or write cycle time (REG[22h] bits [6:5] = 00) 5 t1 ns
Random read or write cycle time (REG[22h] bits [6:5] = 01) 4 t1 ns
Random read or write cycle time (REG[22h] bits [6:5] = 10) 3 t1 ns
t4
CAS# precharge time (REG[22h] bits [3:2] = 00) 2 t1 ns
CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) 1 t1 ns
t5
CAS# setup time (CAS# before RAS# refresh)
0.45 t1 - 2 ns
t6
RAS# precharge time (REG[22h] bits [3:2] = 00) 2.45 t1 - 1 ns
RAS# precharge time (REG[22h] bits [3:2] = 01 or 10) 1.45 t1 - 1 ns
RAS#
CAS#
t4
t6
t5
t2 t3
t1
Memory
Clock
