Epson S1D13504 Manual

next previous

Epson Research and Development Page 5

Vancouver Design Center

Interfacing to the NEC VR4102™ Microprocessor S1D13504

Issue Date: 01/02/02 X19A-G-007-07

List of Tables

Table 3-1: Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 10

Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4-2: Host Bus Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4-2: NEC/S1D13504 Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

List of Figures

Figure 2-1: NEC VR4102 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4-1: Typical Implementation of VR4102 to S1D13504 Interface. . . . . . . . . . . . . . . . 12