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S1D13504F00A Register Summary X19A-Q-001-03
Pa
g
e 2 01/02/02
6 Simultaneous Display Option Selection
7 Number of Bits per Pixel Selection
8 PCLK Divide Selection
9 Suspend Refresh Selection
10 Minimum Memory Timing Selection
11 RAS Precharge Timing Select
Simultaneous Display Option
Select Bits [1:0]
Simultaneous Display Option
00 Normal
01 Line Doubling
10 Interlace
11 Even Scan Only
Number Of Bits/Pixel Select Bits [2:0] Number of Bits/Pixel
000 1
001 2
010 4
011 8
100 15
101 16
110-111 Reserved
PCLK Divide Select Bits [1:0] MCLK/PCLK Frequency Ratio
00 1
01 2
10 3
11 4
Suspend Refresh Select Bits [1:0] DRAM Refresh Type
00 CBR Refresh
01 Self-Refresh
1x No Refresh
RC Timing Bits [1:0] Minimum Random Cycle Width
00 5 MCLK
01 4 MCLK
10 3 MCLK
11 Reserved
RAS Precharge Timing Bits [1:0] RAS Precharge Width
00 2 MCLK
01 1.5 MCLK
10 1 MCLK
11 Reserved