Page 12 Epson Research and Development
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S1D13504 Programming Notes and Examples
X19A-G-002-07 Issue Date: 01/02/01
3 Display Buffer
This section discusses how the S1D13504 stores pixels in the display buffer and where the display
buffer is located.
3.1 Display Buffer Location
The S1D13504 requires either a 512K byte or a 2M byte block of memory to be decoded by the
system. System logic will determine the location of this memory block; the S5U13504B00C evalu-
ation board decodes the display buffer at the 12M byte location of system memory.
3.2 Display Buffer Organization
3.2.1 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades)
Eight pixels are grouped into one byte of display buffer as shown below:
One bit-per-pixel provides two shades of gray by indexing into positions 0 and 1 of the Green Look-
Up Table (LUT) and two levels of color by indexing into positions 0 and 1 of the Red/Green/Blue
LUTs.
3.2.2 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)
Four pixels are grouped into one byte of display buffer as shown below:
Two bit-per-pixel provides four shades of gray by indexing into positions 0 through 3 of the Green
LUT and four levels of color by indexing into positions 0 through 3 of the Red/Green/Blue LUTs.
Table 3-1: Pixel Storage for 1 bpp (2 Colors/Gray Shades) in One Byte of Display Buffer
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Pixel 0
Bit 0
Pixel 1
Bit 0
Pixel 2
Bit 0
Pixel 3
Bit 0
Pixel 4
Bit 0
Pixel 5
Bit 0
Pixel 6
Bit 0
Pixel 7
Bit 0
Table 3-2: Pixel Storage for 2 bpp (4 Colors/Gray Shades) in One Byte of Display Buffer
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Pixel 0
Bit 1
Pixel 0
Bit 0
Pixel 1
Bit 1
Pixel 1
Bit 0
Pixel 2
Bit 1
Pixel 2
Bit 0
Pixel 3
Bit 1
Pixel 3
Bit 0
