Page 12 Epson Research and Development
Vancouver Design Center
S5U13504-D9000 Evaluation Board User Manual
X19A-G-003-05 Issue Date: 01/02/02
3 D9000 Specifics
3.1 Interface Signals
The S1D13504 is intended for direct connection to most processors, so the FPGA in this
environment simply acts as a pass-through for the required processor interface signals.
3.1.1 Connector Pinout for Channel A6 and A7
Table 3-1: Interface Signals
Interface Signals
S1D13504 Signal
Name
Number of
Signals
SH-3 Interface
Signal Name
Generic CPU
Interface
Signal Name
Comments
AB[20:1] 19 A[20:1] A[20:1] Address Bus
AB0 1 A0 A0 Address Bus
DB[15:0] 16 D[15:0] D[15:0] Data Bus
WE1# 1 WE1# WE#1
M/R# 1 External Decode External Decode Memory / Register Select
CS# 1 External Decode External Decode S1D13504 Chip Select
BCLK 1 CKIO BCLK Bus Clock
BS# 1 BS# nc
RD/WR# 1 RD/WR# RD1#
RD# 1 RD# RD0#
WE0# 1 WE0# WE0#
WAIT# 1 WAIT# WAIT#
RESET# 1 RESET# RESET#
5.0V
3.3V
GND
12.0V
XL Touch Screen
XR Touch Screen
YU Touch Screen
YL Touch Screen
XY Touch Screen
Table 3-2: Connector Pinout for Channel A7
Channel A7
Pin # FPGA Signal S1D13504 Signal Pin # FPGA Signal S1D13504 Signal
SmXY
1 chA7p1 BCLK 21 dc5v DC5V
2 chA7p2 N/C 22 GND GND
3 chA7p3 N/C 23 dc3v DC3V
