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Si4421
Application Proposal for LPDM (Low Power Duty-Cycle Mode) Receivers:
16. Low Battery Detector and Microcontroller Clock Divider Command
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR
1 1 0 0 0 0 0 0 d2 d1 d0 0 v3 v2 v1 v0 C000h
The 4-bit parameter (v3 to v0) represents the value V, which defines the threshold voltage V
lb
of the detector:
V
lb
= 2.25 + V · 0.1 [V]
Clock divider configuration:
d2 d1 d0
Clock Output
Frequency [MHz]
0 0 0 1
0 0 1 1.25
0 1 0 1.66
0 1 1 2
1 0 0 2.5
1 0 1 3.33
1 1 0 5
1 1 1 10
The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power
Management Command (page 15).
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