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AN-2030: Digital Diagnostic Monitoring Interface for Optical Transceivers F i n i s a r
9/26/02 Revision D Page 29
2-Wire Interface Reset: After any interruption in protocol, power loss, or system reset,
the following steps reset the DDTC.
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a Start Condition while SDA is high.
Device Addressing: The DDTC must receive an 8-bit device address word following a
start condition to enable a specific device for a read or write operation. The address
word is clocked into the DDTC MSB to LSB. The address word is 1010000Xb, where X
is the Read/Write (R/W) bit. If the R/W bit is high (1), a read operation is initiated. If
R/W is low (0), a write operation is initiated.
Write Operations: After receiving a matching address byte with the R/W bit set low, the
device goes into the write mode of operation. The master must transmit an 8-bit
EEPROM memory address to the device to define the address where the data is to be
written. After the reception of this byte, the DDTC will transmit a zero for one clock
cycle to acknowledge the receipt of the address. The master must then transmit an 8-
bit data word to be written into this address. The DDTC will again transmit a zero for
one clock cycle to acknowledge the receipt of the data. At this point the master must
terminate the write operation with a stop condition for the write to be initiated. If a start
condition is sent in place of the stop condition, the write is aborted and the data
received during that operation is discarded. If the stop condition is received, the DDTC
enters an internally timed write process T
w
to the EEPROM memory. The DDTC will not
send an acknowledge bit for any two wire communication during an EEPROM write
cycle.
The DDTC is capable of an 8-byte page write. A page is any 8-byte block of memory
starting with an address evenly divisible by eight and ending with the starting address
plus seven. For example, addresses 00h through 07h constitute one page. Other pages
would be addresses 08h through 0Fh, 10h through 17h, 18h through 1Fh, etc.
A page write is initiated the same way as a byte write, but the master does not send a
stop condition after the first byte. Instead, after the slave acknowledges receipt of the
data byte, the master can send up to seven more bytes using the same nine-clock
sequence. The master must terminate the write cycle with a stop condition or the data
clocked into the DDTC will not be latched into permanent memory.
The address counter rolls on a page during a write. The counter does not count through
the entire address space as during a read. For example, if the starting address is 06h
and 4 bytes are written, the first byte goes into address 06h. The second goes into
address 07h. The third goes into address 00h (not 08h). The fourth goes into address
01h. If more than 9 or more bytes are written before a stop condition is sent, the first
bytes sent are over-written. Only the last 8 bytes of data are written to the page.