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43 Chapter 4
/***** Set Pacer *****/
outportb(base_addr+0x0f,0x7E); //Pacer=1M/clk1/clk2
outportb(base_addr+0x0d,0x0A); //clk1
outportb(base_addr+0x0d,0x00); //10=0x0A ; 100=0x64 ;
1000=0x3E8
outportb(base_addr+0x0f,0xBE);
outportb(base_addr+0x0e,0x0A); //clk2
outportb(base_addr+0x0e,0x00);
/***** Pacer=1M/10/10=10k ******/
/***** Set ISR *****/
Add you code here
/********************/
/***** Set Interrupt *****/
Add you code here
/********************/
outportb(base_addr+8,0); //Clear Interrupt
outportb(base_addr+9,0xf3); //Set Pacer Trigger and Enable INT
/***** Ready for Data Acquisition *****/
while(i<AD_NO)
{
while(iflag==0) {;}//Wait for Interrupt
ad_lb=inportb(base_addr+0); //Get A/D LowByte
ad_hb=inprrtb(base_addr+1);//Get A/D HighByte
i++
}
/***** END *****/
}