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TMP92CZ26A
92CZ26A-302
3.13.3 SFR
TMRB0 RUN Register
7 6 5 4 3 2 1 0
Bit symbol TB0RDE − I2TB0 TB0PRUN TB0RUN
Read/Write R/W R/W R/W R/W R/W
After Reset 0 0 0 0 0
TMRB0
prescaler
Up counter
(UC10)
Function
Double
buffer
0: disable
1: enable
Always
write “0”
In IDLE2
mode
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
Note: The 1, 4 and 5 of TB0RUN are read as “1” value.
TMRB1 RUN Register
7 6 5 4 3 2 1 0
Bit symbol TB1RDE − I2TB1 TB1PRUN TB1RUN
Read/Write R/W R/W R/W R/W R/W
After Reset 0 0 0 0 0
TMRB1
prescaler
Up counter
(UC12)
Function
Double
buffer
0: disable
1: enable
Always
write “0”
In IDLE2
mode
0: Stop
1: Operate
0: Stop and clear
1: Run (Count up)
Note: The 1, 4 and 5 of TB1RUN are read as “1” value.
Figure 3.13.3 Register for TMRB (1)
Count operation
0 Stop and clear
<TB0PRUN>, <TB0RUN>
1 Count up
Count operation
0 Stop and clear
<TB1PRUN>, <TB1RUN>
1 Count up
TB0RUN
(1180H)
TB1RUN
(1190H)