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Architecture
154
LWR Load Word Right (cont.) LWR
It is alright to put a load instruction that uses the same rt as the LWR instruction immediately before
LWR. The contents of general-purpose register rt are bypassed internally in the processor,
eliminating the need for a NOP between the two instructions.
No Address Error instruction is raised due to misalignment.
Operation :
T:
vAddr ← ((offset
15
)
16
||
offset
15..0
)
+ GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
31..2
|| (pAddr
1..0
xor ReverseEndian
2
)
if BigEndianMem = 1 then
pAddr ← pAddr
31..2
|| 0
2
endif
byte ← vAddr
1..0
xor BigEndianCPU
2
mem ← LoadMemory (uncached, WORD-byte, pAddr, vAddr, DATA)
GPR[rt] ← mem
31..32-8*byte..0
|| GPR[rt]
31-8*byte..0
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)
Address Error exception