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TMP92CZ26A
92CZ26A-613
Table 3.23.1 Relationships between Analog Input Channels and AD Conversion Result Registers
AD Conversion Result Registers
Analog Input Channel
(Port G)
Conversion Modes
other than at right
Channel Fixed Repeat
Conversion Mode
(every fourth conversion)
AN0 ADREG0H/L
AN1 ADREG1H/L
AN2 ADREG2H/L
AN3 ADREG3H/L
AN4 ADREG4H/L
AN5 ADREG5H/L
A
DREG0H/L
A
DREG3H/L
A
DREG1H/L
A
DREG2H/L
Note: For detect a overrun error thoroughly, read the AD conversion result register high at first and
read the AD conversion result register low at second. If OVRn=”0” and ADRnRF=”1”, a
correct conversion result was obtained.
3.23.2.9 Data Polling
When the results of AD conversion are processed by means of data polling without
using interrupts, ADMOD0<EOS> should be polled. After confirming ADMOD0
<EOS>=”1”, read the AD conversion result register.